The present invention relates to a semiconductor device, and particularly to a semiconductor device that continuously accesses irregular addresses in a memory.
Countries adopt different broadcast systems in wireless communications such as television broadcasting. However, in order to develop a receiver (television and recorder, for example) that supports multiple wireless systems, there is a problem of increasing development and manufacturing cost when development of such a receiver is advanced for each broadcast system. Accordingly, there is an increasing demand for semiconductor devices that perform wireless processes in the receiver performing such wireless communications to include a multi-standard feature supporting multiple broadcast systems. Further, such a receiver is requested to include a multi-channel feature that receives multiple broadcast channels simultaneously and allows viewing or recording of multiple programs simultaneously. Therefore, there also is an increasing demand for the semiconductor device to include the multi-channel feature that processes multiple programs at the same time.
However, in order to realize all the functions supporting the multi-standard and multi-channel features by hardware, there is a problem in the circuit size that increases along with the number of broadcast systems and the number of channels to be processed simultaneously so as to process individual broadcast systems and multiple channels. This lead to the suggestion of software-defined radio that realizes the multi-standard and multi-channel features by software operating on a DSP (Digital Signal Processor).
The software-defined radio performs a demodulation process of wireless signals. In this demodulation process, it is necessary to perform a decoding process represented by a deinterleave process that rearranges complicated data across a wide range on a time axis. More specifically, the deinterleave process needs to perform irregular memory accesses according to continuous stream processes. Note that the deinterleave process is a reverse process of an interleaving process performed by a transmitter side, and the format of data arrangement in the deinterleave process is determined depending on the interleaving processes by the transmitter side.
However, it is difficult for a common DSP to perform such irregular and continuous memory accesses due to limited processing capacity. Thus, Japanese Unexamined Patent Application Publication Nos. 59-114655 and 03-260750 disclose a technique for efficiently performing irregular and continuous memory accesses.
Japanese Unexamined Patent Application Publication No. 59-114655 discloses a data transfer device that transfers data from a first memory region to a second memory region. This data transfer device includes a central processing unit, the first storage device, the second storage device, storage means, address generate and supply means, and address read and supply means.
Data to be transferred is stored to the first storage device. The second storage apparatus stores the data to be transferred. The storage means stores a correspondence table between an address in the first storage device and an address in the second storage device for each data to be transferred. Upon receipt of a read start address of data in the first storage device from the central processing unit, the address generate and supply means supplies the first storage device with a read address for each data to be transferred. Upon receipt of the read start address of the data in the first storage device, the address read and supply means reads from the storage means an address in the second storage device that corresponds to the read address in the first storage device, and supplies the second storage device with the address as a write address.
That is, the data transfer device disclosed in Japanese Unexamined Patent Application Publication No. 59-114655 converts the read address in the first storage device into the write address in the second storage device using the correspondence table. In this way, the data transfer device disclosed in Japanese Unexamined Patent Application Publication No. 59-114655 is capable of efficiently writing data to the address in the second storage device that is different from the read address in the first storage device.
Japanese Unexamined Patent Application Publication No. 03-260750 discloses a DMA (Direct Memory Access) transfer method that performs data transfer among multiple storage devices using a central processing unit and a DMA controller. The technique disclosed in Japanese Unexamined Patent Application Publication No. 03-260750 includes a conversion table that converts continuous addresses of a transfer destination supplied from the DMA controller into non-continuous addresses for accessing multiple storage devices, a conversion table that converts the addresses of a transfer source into non-continuous addresses, and an address conversion unit that converts the addresses output from the DMA controller using both conversion tables into real addresses.
That is, in the technique disclosed in Japanese Unexamined Patent Application Publication No. 03-260750, the conversion table and the address conversion unit convert the addresses output from the DMA controller into addresses that are different between the transfer source addresses and the transfer destination addresses. In this way, Japanese Unexamined Patent Application Publication No. 03-260750 disclose a technique that realizes efficient data transfer to the transfer destination with the address different from the transfer source address.